The present invention relates generally to a semiconductor integrated circuit device, and more particularly to an integrated circuit device provided with elements for protecting the circuit from overvoltage.
In order to protect circuits from overvoltages such as surge voltages in a semiconductor integrated circuit device, it has been the conventional method for input terminals, output terminals, supply voltage terminals, etc. to be connected to a ground terminal via protective elements which are short-circuited in response to overvoltage to prevent overcurrent from flowing through the circuits. These protective elements are bipolar transistors, field transistors, MOS transistors, etc.
In this conventional method, however, where the circuit has two or more combinations of supply voltage terminals and corresponding ground terminals, it has been required that each input terminal and each output terminal be connected to all the ground terminals via protective elements, and furthermore for the supply voltage terminals to be connected to the ground terminals via protective elements. This is because it is necessary for all the input and output terminals to be resistant against predetermined overvoltages (referred to as ESD withstand voltages, hereinafter), in every case where any one of the ground terminals and the supply voltage terminals is determined as a reference potential terminal.
However, when each input terminal and each output terminal are connected to all the ground terminals via protective elements and furthermore all the supply voltage terminals are connected to the ground terminals via protective elements, there exists a problem in that the number of combinations of protective elements increases and therefore the chip area increases, thus resulting in a more complicated wiring arrangement and thereby a higher device cost.